A basic phase-locked loop (PLL) is a circuit which produces an output signal synchronized to an input reference signal. A PLL output signal is synchronized or "locked" to a reference signal when the frequency of the output signal is the same as that of the reference signal. Under locked conditions, a PLL may provide for a constant phase difference between the reference and output signals. This phase difference may assume any desired value including zero. Should a deviation in the desired phase difference of such signals develop (i.e., should a phase error develop) due to, e.g., variation in either (i) the frequency of the reference signal or (ii) programmable parameters of the PLL, the PLL will attempt to adjust the frequency of its output signal to drive the phase error toward zero.
There are several different types of PLLs. Among these are PLLs which are charge pump-based. In a charge pump-based PLL, a phase-frequency detector compares an input reference signal to an output signal from a voltage controlled oscillator for the purpose of observing phase and frequency differences between the signals. If differences are observed, the phase-frequency detector produces logic pulses indicative of such differences. A charge pump receives these logic pulses and, based thereon, provides pulses of current to a loop filter and ultimately the voltage controlled oscillator. As filtered, these current pulses serve to adjust the voltage controlled oscillator to compensate for the observed differences.
The magnitude of PLL bandwidth is a parameter affecting PLL performance. The larger the bandwidth, the larger the steady-state phase jitter (i.e., the larger the phase error due to circuit noise) of the PLL but the smaller the settling time for variations in the reference signal or PLL parameters (i.e., the smaller the time needed by the PLL to adjust to the variations). The smaller the PLL bandwidth, the smaller the steady-state phase jitter, but the larger the settling time. Consequently, a PLL design trade-off issue can exist between desirable values of steady-state phase jitter and reference signal/PLL parameter variation settling time.